Important DFT questions

TOP 10 : DFT Questions


1. What is Scan Chain Methodology ? Can you explain in a detailed manner



2. MSV ? Macro Structures Verification ?




3. Why TRST in 1149 Mode is a Optional Pin ?



4. Difference between Extest and Sample/Preload Instructions in 1149 Mode ?



5. What is the Functionality of the Locked Up Latch



6. What are the criteria of the Test Selections for a Clock Gating Circuitry ?



7. Can you explain Basic DFT Flow ?



8. Scan chain Reordering and Why is it needed ?



9. LSSD ?



10. Advantages and Disadvantages of the Muxed and LSSD Scan approaches ?



Please post your answers

DFT classification

DFT can be divided in the following sections :

1. Combinational Testing
2. Scan Test Methodology
3. Boundary Scan
4. BIST
5. ATPG
6. Patterns Simulation
7. Low Power Testing

Controllability : How Easy or difficult to force a particular value of a Node so that It can be justified through Primary Inputs

Obseravbility : How Easy or Difficult is to force a particular value of a node so that It can be seen at directly Obseravable Outputs

VLSI DISCUSSION

Hi ,

We can have a VLSI discussion through this Blog
We will include the Topics which are relevant to the VLSI working areas like
DFT , PD , VERIFICATION , DESIGN and Others .

Thanks and Regards
Kshitij Kulshreshtha