DFT NEW QUESTIONS

1. What are the false and multicycle paths ?

2. For at speed patterns : What addtional care need to be taken in terms of timing exceptions while doing at speed testing ?

3. What are the traditional methods to counteract against the false and multicycle paths for the at speed testing ?

4. What is the new method for the at speed patterns creation with timing exceptions ?

5. Why are the Cutpoints added for ASST?

6. Can you explain on-Product clock generation circuitry ?

MACRO TESTING

MACRO TESTING:

->Two Important Phases of the Macro Testing

Macro Test uses a data Independent access scheme.

It is done is two major stages

First Phase is MSV

MSV Tool generates the correspondence solutions for all the relevant macros and macro Operations.

The Correspondence solutions will comprise of the necessary pre-conditioning data

and global pattern templates for the actual test data.

Second Phase: MTG Phase

MTG (Macro Test Generation) combines the local macro-level test data with the

Correspondence solution to generate the global test data for the macros.

Basic Design Flow for MTEST:

1. Read the Netlist

2. Read the MIC file

3. Do the MSV

4. Analyze the MSV messages and Debug in case of errors

5. MTG phase will start

6. Read the MPR file

7. Generate the Macro Test Data

Detailed Description of the MSV Phase

- MSV tool will read the netlist and testmode information. It has to find all the Macros that must be processed for the given test-mode.

- Every Macro must be associated with MIC file

- MIC file defines the macro-specific operations and access requirements.

- MSV will try to find pre-conditioning and correspondence solutions for each macro operation

- For each macro data Input/output, the tool will try to find a suitable correspondence point and sensitize a path.

- Path Sensitization will be done by an ATPG tool that justifies the path side inputs back to appropriate pre-conditioning values.

- MIC file describes the Nature of the senitized or allowed path and pre-conditioning constraints for each macro pin.

- Correspondence solutions will be generated in Binary or text formats

Detailed Description of the MTG Phase

MTG tool reads the binary form of the correspondence solution and the associates Macro Patter Rule (MPR) file.

MPR file contains the macro level test data that are to be plugged into the global pattern templates defined by the correspondence solutions.

Resulting Macro test data are then written into the test data file for the chip

MPR file

C programs that use MTG specific commands to assign the data values to the PINGROUPS defines in operations for the Algorithm represented by the MPR

Basic Concept of MTEST

To Provide Test Stimuli to the Macro Inputs, a logic path is sensitized between each relevant macro data input and a corresponding controllable Test Port in the top level design.

To receive the test responses from the macro outputs, a logic path is sensitized between each macro outputs; a Logic path is sensitized between each macro output

and corresponding observable Top in the top level design.

Probable Test Sequence

The test sequence:

1. Force PI

2. Apply the clocks

3. Drop LTEST: go into the Functional Mode

4. Do the Required Testing in Functional Mode

5. Raise the LTEST and then Scanned out the Responses

Important DFT questions

TOP 10 : DFT Questions


1. What is Scan Chain Methodology ? Can you explain in a detailed manner



2. MSV ? Macro Structures Verification ?




3. Why TRST in 1149 Mode is a Optional Pin ?



4. Difference between Extest and Sample/Preload Instructions in 1149 Mode ?



5. What is the Functionality of the Locked Up Latch



6. What are the criteria of the Test Selections for a Clock Gating Circuitry ?



7. Can you explain Basic DFT Flow ?



8. Scan chain Reordering and Why is it needed ?



9. LSSD ?



10. Advantages and Disadvantages of the Muxed and LSSD Scan approaches ?



Please post your answers

DFT classification

DFT can be divided in the following sections :

1. Combinational Testing
2. Scan Test Methodology
3. Boundary Scan
4. BIST
5. ATPG
6. Patterns Simulation
7. Low Power Testing

Controllability : How Easy or difficult to force a particular value of a Node so that It can be justified through Primary Inputs

Obseravbility : How Easy or Difficult is to force a particular value of a node so that It can be seen at directly Obseravable Outputs

VLSI DISCUSSION

Hi ,

We can have a VLSI discussion through this Blog
We will include the Topics which are relevant to the VLSI working areas like
DFT , PD , VERIFICATION , DESIGN and Others .

Thanks and Regards
Kshitij Kulshreshtha